Flash memories   NOR / NAND

NOR memories

Reading from NOR flash is similar to reading from random-access memory, provided the address and data bus are mapped correctly. Because of this, most microprocessors can use NOR flash memory as execute in place (XIP) memory, meaning that programs stored in NOR flash can be executed directly without the need to copy them into RAM. NOR flash chips lack intrinsic bad block management, so when a flash block is worn out, the software or device driver controlling the device must handle this, or the device will cease to work reliably.

When unlocking, erasing or writing NOR memories, special commands are written to the first page of the mapped memory. These commands are defined by the Common Flash memory Interface (CFI) and the flash chips can provide a list of available commands to the physical driver.

Apart from being used as random-access ROM, NOR memories can also be used as storage devices. However, NOR flash chips typically have slow write speeds compared with NAND flash.

NAND memories

NAND flash memories cannot provide execute in place due to their different construction principles. These memories are accessed much like block devices such as hard disks or memory cards. The pages are typically 512 or 2,048 bytes in size. Associated with each page are a few bytes (typically 12–16 bytes) that should be used for storage of an error detection and correction checksum.

The pages are typically arranged in blocks. A typical block would be 32 pages of 512 bytes or 64 pages of 2,048 bytes.

While programming is performed on a page basis, erasure can only be performed on a block basis.

NAND devices also require bad block management to be performed by device driver software, or by a separate controller chip (SD cards, for example, include controller circuitry to perform bad block management and wear leveling). When a logical block is accessed by high-level software, it is mapped to a physical block by the device driver or controller, and a number of blocks on the flash chip are set aside for storing mapping tables to deal with bad blocks.

The error-correcting and detecting checksum will typically correct an error where one bit per 256 bytes is incorrect. When this happens, the block is marked bad in a logical block allocation table, and its undamaged contents are copied to a new block and the logical block allocation table is altered accordingly. If more than one bit in the memory is corrupted, the contents are partly lost, i.e. it is no longer possible to reconstruct the original contents.

Most NAND devices are shipped from the factory with some bad blocks which are typically identified and marked according to a specified bad block marking strategy. By allowing some bad blocks, the manfacturers achieve far higher yields than would be possible if all blocks were tested good. This significantly reduces NAND flash costs and only slightly increases the size of the parts.

The first physical block (block 0) is always guaranteed to be readable and free from errors. Hence, all vital pointers for partitioning and bad block management for the device must be located inside this block (typically a pointer to the bad block tables etc). If the device is used for booting a system, this block may contain the master boot record.

When executing software from NAND memories, virtual memory strategies are used: memory contents must first be paged or copied into memory-mapped RAM and executed there. A memory management unit (MMU) in the system is helpful, but this can also be accomplished with overlays. For this reason, some systems will use a combination of NOR and NAND memories, where a smaller NOR memory is used as software ROM and a larger NAND memory is partitioned with a file system for use as a random access storage area. NAND is best suited to flash devices requiring high capacity data storage. This type of flash architecture combines higher storage space with faster erase, write, and read capabilities over the execute in place advantage of the NOR architecture.

The distinction between NOR and NAND flash

NOR and NAND flash differ in two important ways:

• the connections of the individual memory cells are different
• the interface provided for reading and writing the memory is different (NOR allows random-access for reading, NAND allows only block access) It is important to understand that these two are linked by the design choices made in the development of NAND flash. An important goal of NAND flash development was to reduce the chip area required to implement a given capacity of flash memory, and thereby to reduce cost per bit and increase maximum chip capacity so that flash memory could compete with magnetic storage devices like hard disks.

NOR and NAND flash get their names from the tructure of the interconnections between memory cells. In NOR flash, cells are connected in parallel to the bit lines, allowing cells to be read and programmed individually. The parallel connection of cells resembles the parallel connection of transistors in a CMOS NOR gate. In NAND flash, cells are connected in series, resembling a NAND gate, and preventing cells from being read and programmed individually: the cells connected in series must be read in series.

Because of the series connection, a large grid of NAND flash memory cells will occupy only a small fraction of the area of equivalent NOR cells (assuming the same CMOS process resolution, e.g. 130 nm, 90 nm, 65 nm). NAND flash's designers realized that the area of a NAND chip, and thus the cost, could be further reduced by removing the external address and data bus circuitry. Instead, external devices could communicate with NAND flash via sequential-accessed command and data registers, which would internally retrieve and output the necessary data. This design choice made random-access of NAND flash memory impossible, but the goal of NAND flash was to replace hard disks, not to replace ROMs.

Endurance

The endurance of NAND flash is much greater than that of NOR flash (typically 1,000,000 cycles vs. 100,000 cycles). This is because programming and erasure in NOR flash rely on different microscopic processes (hot electron injection and quantum tunneling, respectively), while they are perfectly symmetric in NAND flash (Fowler-Nordheim tunneling). The asymmetric nature of NOR flash programming and erasure increases the rate at which memory cells degrade, over many program/erase cycles.

The superior symmetric programming method of NAND flash has in fact been adopted in many NOR flash designs, so that some modern NOR chips boast endurance comparable to NAND flash.